CCD transversal filter using weighted input

ABSTRACT

An analog transversal filter includes a charge transfer delay line, including a plurality of cells for storing electrical charge, and a multiphase clock to transfer electrical charge from cell to cell through the delay line. A plurality of injection electrodes are connected to predetermined ones of the cells to sample an electrical signal, weight the signal sample a predetermined amount, and inject a charge packet representing the weighted signal sample into the cell. An output electrode collects and sums the charge packets transferred through the delay line. In another embodiment, the filter includes a plurality of charge transfer delay lines, with a plurality of cells for storing electrical charge in each delay line. A third embodiment includes a charge transfer delay line with a plurality of stages, each stage including a plurality of cells for storing electrical charge such that the cells of each stage are wider, in a direction transverse to the direction of charge transfer in the delay line, than the cells of preceding stages within the delay line. A plurality of end injection electrodes, each connected to one of the stages, and a plurality of side injection electrodes, each connected to a predetermined one of the cells, sample the signal, weight the signal sample a predetermined amount, and inject a charge packet representing the weighted signal sample into the stage or the cell, respectively.

GOVERNMENT RIGHTS

The Government has rights in this invention pursuant to a contractawarded by the Department of the Air Force.

BACKGROUND OF THE INVENTION

This invention concerns the field of charge coupled device (CCD)transversal filters.

Charge coupling is the collective transfer, by the external manipulationof voltages, of all the mobile electric charge stored within asemiconductor storage element to a similar, adjacent storage element.Majority carriers (or their absence) may be stored in a spatiallydefined depletion region (a potential well) at the surface of ahomogeneous semiconductor. A potential well is a localized volume in thesemiconductor substrate which, because it is the most positive location,is attractive to a negative electrons. Charge coupling is particularlyuseful in processing signal information because the amount of electricalcharge which is contained in each charge packet can be used to representinformation.

Packets of electrical charge move through a CCD as a result of acontinuous lateral displacement of the local potential wells. Apotential well is moved by applying a periodic waveform, called theclock voltage, to electrodes on the CCD. Under the influence of theclock voltage, some of the electrons in the vicinity of each electrodeform a discrete packet of charge and move from one charge coupledelement, or unit cell, to the next cell for each full clock cycle.

A CCD array is well suited as a time sample analog shift register, i.e.,a delay line in which the time delay is proportional to thereadin/readout rate. CCDs are inherently analog and thus can readilyperform sampled data filtering functions in the analog domain.Furthermore, the analog nature of the CCD makes it possible to storemore than one data bit in each memory cell and affords a CCD aninherently large dynamic range.

Any signal processing task involving the linear transformation of analogsignals, such as correlation, discrete Fourier transforms, filter banks,matched filtering, multiplexing/demultiplexing, array scanning,orthogonal scan transformations, time base translations, etc., can berealized with CCDs. In sampled data filtering functions, for example,data is sampled at a certain frequency and the samples are operated onto produce a desired output. In this application, a CCD is advantageousover more conventional delay lines because of its wide dynamic range andbecause the propagation velocity and the delay time can be separatelycontrolled. Sampled data filtering has typically been done in the priorart by fabricating a delay line with interim taps at which the signal issensed and fed back to earlier stages to affect the transmission of thedata. Such a structure can be conveniently configured as a bandpassfilter where the resonant frequency of the circuit is a direct functionof the clock frequency.

Analog-to-digital conversion is expensive and complicated when a largedynamic range (8 or more bits) is required in conjunction with a largebandwidth (5 MHz or more). By using a CCD, sampled data filtering can beperformed in the analog domain, thereby eliminating the need for ananalog-to-digital conversion and simplifying the associated electronics.The control of the CCD by a master clock also permits a high degree ofsynchronization and stability. Furthermore, the time delays involved areinsensitive to temperature and component drift. All these factorssupport the choice of an analog CCD implementation over digitalapproaches to signal processing.

In a serial in/parallel out filtering function, independent,nondestructive low impedance voltage readouts of analog signals areaccomplished at specified locations or taps along the CCD, correspondingto various delays through the CCD shift register. The signal voltagewhich is measured at each tap may be multiplicatively weighted byconductance to give a current proportional to the product of the signalvoltage and the weighting conductance. The summation of these productcurrents can then provide such functions as transversal filtering,correlation, or sampled data smoothing. A two dimensional weightingmatrix driven by independent low impedance taps can be used for discreteFourier transformers, filter banks, or multiple cross correlators.Electrically reprogrammable analog weights combined with these buildingblocks can be used in adaptive filtering for communicationsapplications. The use of programmable conductances, such as withnonvolatile MNOS or conventional MOS devices, permits such applicationsas an adaptive transversal line equalizer or a programmable matchedfilter. Such matched filters are used in wide spectrum communicationssystems and in radar to detect weak signals in high noise backgrounds.

In such a transversal CCD filter, each delay stage in the CCD representsone clock period of CCD delay. The input signal is nondestructivelysampled at each stage, multiplied by weighting coefficients, and theproducts are summed. The resulting output is in the form of a sampleddata convolution of the input signal with the filter coefficients.

The transversal CCD filters which are known in the art have typicallybeen implemented with a split electrode, which is either a drivenelectrode or a floating electrode extending across the width of the CCD.A split electrode provides weighting by dividing up the current due tocharge passing beneath the electrode. The split electrode technique,however, has been implemented in silicon technology and at frequenciesmuch lower than 25 MHz. With the advent of faster semiconductortechnologies, such as III-V GaAs devices, a need has developed for a newtransversal filter CCD architecture which will operate with improvedaccuracy and additional immunity to noise.

SUMMARY OF THE INVENTION

In one embodiment, the analog transversal filter of this inventionincludes a charge transfer delay line, including a plurality of cellsfor storing electrical charge, and a multiphase clock to transferelectrical charge from cell to cell through the delay line. A pluralityof injection electrodes are connected to predetermined ones of the cellsto sample an electrical signal, weight the signal sample a predeterminedamount, and inject a charge packet representing the weighted signalsample into the cell. An output electrode collects and sums the chargepackets transferred through the delay line.

In another embodiment, the filter includes a plurality of chargetransfer delay lines, with a plurality of cells for storing electricalcharge in each delay line and a multiphase clock for transferringelectrical charge from cell to cell through each delay line. A pluralityof injection electrodes is each connected to one of the delay lines tosample the signal, weight the signal sample a predetermined amount, andinject a charge packet representing the weighted signal sample into thedelay line. An output electrode collects and sums the charge packetstransferred through the delay lines.

A third embodiment includes a charge transfer delay line with aplurality of stages, each stage including a plurality of cells forstoring electrical charge such that the cells of each stage are wider,in a direction transverse to the direction of charge transfer in thedelay line, than the cells of preceding stages within the delay line. Amultiphase clock transfers electrical charge from cell to cell throughthe delay line. A plurality of end injection electrodes, each connectedto one of the stages, and a plurality of side injection electrodes, eachconnected to a predetermined one of the cells, sample the signal, weightthe signal sample a predetermined amount, and inject a charge packetrepresenting the weighted signal sample into the stage or the cell,respectively. An output electrode collects and sums the charge packetstransferred through the delay line.

BRIEF DESCRIPTION OF THE DRAWINGS

Additional details of the invention are presented below in thedescriptive section, which refers to the drawings, where:

FIG. 1 is a schematic diagram illustrating the operation of the CCDtransversal of this invention;

FIG. 2 schematically depicts a monolithic implementation of a halfbanding filter constructed according to this invention;

FIG. 3(a)-3(c) are a graphical depiction of the three filteringfunctions for which the filter of FIG. 2 can be configured;

FIG. 4 is a plan view of a semiconductor mask layout for the half-bandfilter of FIG. 2, implemented with end injection signal sampling;

FIG. 5 is a potential diagram illustrating the operation of an inputsampling scheme for the filter of FIG. 2; and

FIG. 6 is a plan view of an alternative mask layout for the filter ofFIG. 2.

DESCRIPTION OF THE INVENTION

FIG. 1 is a schematic diagram illustrating the novel manner in which theCCD transversal filter of this invention operates. The technique isimplemented with a charge sampling electrode at each input point in thedelay line of the filter. Charge sampling is accomplished at the inputpoints 102, 104, 106, 108, 110, 112 . . . 114 for cells 116, 118, 120,122, 124, 126 . . . 128 of a CCD delay line 100. The input signal f(t)is subjected to a weighting function, whose coefficients for the cells116-128 are represented by h_(n) . . . h_(n+N). After the weighting isapplied to the signal, the weighted signal is injected into the CCD atthe input points 102-114. This arrangement contravenes prior arttechniques in which sampling is achieved by first tapping the delay lineat multiple output points and then applying weighting to these outputs.Thus the CCD channel itself, contrary to prior art approaches,accomplishes the summing of the weighted charge signals. The weightedsignal portions are clocked through the delay line by the phases 130,132, and 134 of a multiphase clock 136. The final summation ##EQU1##(where h(n) is the weighting function and T is the sampling period) ofthis filtering function is achieved at the output node 138 of the CCD100.

The CCD transversal filter of this invention has been used in oneembodiment to implement a Finite Impulse Response (FIR) transversalhalf-band filter. This filter chip helps to integrate the threefunctions of communications, navigation, and identification into asingle piece of equipment. The filter acts as a frequency selectiondevice which can be rapidly changed to select different frequencies inthe VHF band, so that time division multiplexing may be used to obtainall three functions. In one implementation, the CCD filter chip is partof an agile bandpass filter for signals in the VHF band (30 to 400 MHz)of fairly moderate strength. The filter stage will accept signals over abroad bandwidth, determined by the sampling and clocking frequency ofthe CCD devices, and it will select which half of the input bandwidth isallowed to pass through to the output port.

The design of the half-band sections calls for an impulse response foreither the low or high pass frequencies. An outstanding feature of thishalf-band filter is that the magnitudes of the tap weights are constantand match exactly for the respective delays in both types. Thus only thesigns of the side taps in the real or in-phase signal paths need bechanged to select a different output response.

Tap weight values are calculated using the basic Sin(x)/x functioncorresponding to the selected value of bandwidth, with the necessary bitlength of the transversal filter determined by the transition frequencybandwidth. The tap weight values are obtained by multiplying thesequantities by a McClellan algorithm window function (See McClellan, etal., A Computer Program for Designing Optimum FIR Linear Phase DigitalFilters, IEEE Transactions on Audio and Electroacoustics, Volume AU-21(December 1973)). The added detail necessary to distinguish the low passfrom the high pass and the real from the quadrature path is provided bythe complex multiplier for each of the upper and lower bandconfigurations. The lower band configuration is basically a bandpassconfiguration, but with a very low center frequency (sampling frequencydivided by 8).

A low pass filter can be changed to a high pass filter with the samecutoff frequency simply by using the complement of the input signal.Convolution is achieved by summing the weighted, time-delayed versionsof the signal. The maximum attenuation must be maintained by havingaccurate weighting coefficients. For proper operation, a FIR transversal(half-band) filter requires weighted sampling of the input signal atfixed delay intervals, plus accurate summing of those samples.

All the functions required in an n samples FIR filter can be implementedwith n CCDs. The required sampling is obtained by using the CCDs toconvert the input signal into charge packets, while the area of theinput gate for each CCD determines the relative weight of each sample.The various required delays are obtained by routing the input signalthrough CCDs having different numbers of cells, with each CCD cellproviding one clock period of delay. The charge transferred through allthe CCDs in the filter is brought together at a single output node,where the total amount of charge is converted back into a voltagesignal. Since the charge packets arriving at the output nodes of theCCDs have each undergone different time delays, the output voltage iseffectively a sum of weighted time domain samples.

FIG. 2 depicts a monolithic implementation of a half banding filter withall the support circuitry included. There are two CCD devices, each in a"pipe organ" configuration. One set of CCDs is for the real path, whilethe other is for the quadrature path. In addition, the necessary supportcircuitry is included to output a nonsampled signal.

In operation the input signal is applied on an input line 200 to abalanced amplifier 202, which generates complementary signals 204 and206. Complementary signals must be used to satisfy the requirement forpositive (the signal 204) and negative (the signal 206) tap weights inthe filter. When this technique is used with very small signals, theCCDs are quiescently biased to have a half full-charge propagating inthe device at all times. The signals 204 and 206 are routed to theproper input gates of the CCDs through a MESFET switch 208, which isused to select the desired band and provides the programmability of thefilter. A pulse generator circuit 210 produces subnanosecond pulses forinput sampling control. The pulses from the circuit 210 are used tocreate samples at the input of each CCD.

In the particular embodiment shown here, there are seven real inputs212-224 and six imaginary inputs 226-236. The real group includes theseven CCDs 238-250 and the imaginary or quadrature group includes thesix CCDs 252-262. These two CCD groups provide the building blocks for acomplex transversal filter. The imaginary group is connected to exhibita band pass response, while the real CCD group is switchable (by meansof the MESFET switch 208) between functioning as a low pass filter andas a high pass filter.

Since this particular embodiment of the inventive filter requires onlyseven tapping points, it is a relatively simple example of a transversalfilter. The pipe organ approach is appropriate where only a few separateCCDs are used. The pipe organ combination of the seven CCDs 238-250which constitutes the real (in phase) path transversal filter performsdelay, weighting, and summation tasks for each of the seven taps.Weighting is accomplished through determining the amount of charge thatcould be formed (relatively) in the CCD with the appropriate delay.Summation is achieved by dumping all the charge into one capacitivenode. The CCD outputs are monitored by two track and hold circuits 264and 266, with a second pulse generator circuit 268 providing track andhold control. The pulses from the circuit 268 trigger the track-and-holdcircuits to reconstruct the input signal while removing sampling andclocking feedthrough.

FIG. 3 is a graphical depiction of the three filtering functions forwhich the filter of FIG. 2 can be configured. The horizontal axis ineach plot represents the relative time delay for each injection of asignal sample into a CCD, while the numbers associated with that axisindicate the CCD of FIG. 2 into which the sample is injected for eachtime delay. The vertical axis represents the relative weighting(positive or negative) which is applied to each injected signal sample.FIG. 3a depicts the weighted sampling scheme which will configure thereal CCD group 238-250 to operate as a low-pass filter, while FIG. 3bdepicts the sampling scheme for the high-pass configuration of the realCCD group. FIG. 3c similarly indicates the weighted sampling which isapplied by the quadrature CCD group 252-262 to achieve band-passfiltering.

FIG. 4 is a plan view of a mask layout for the half-band filter of FIG.2, implemented with end injection signal sampling. Clock signals forphases 1, 2, 3, and 4 of the CCD are provided on lines 400, 402, 404,and 406, respectively. Each gate of the CCD is provided with three linesto perform the input function. The input sampling pulses are applied,for the real half of the filter, to the lines 408, 410, 412, 414, 416,418, and 420. The reference (the input transfer gate) is applied tolines 422, 424, 426, 428, 430, 432, and 434.

The signal to be filtered, referenced to the transfer gate, is appliedto the appropriate cell of the CCD by the input lines 436, 438, 440,442, 444, 446, and 448. Those input lines which are always positivelyweighted, such as the input line 442, are supplied by the constantpositive line 450. Similarly, the input lines which are alwaysnegatively weighted are connected to the constant negative line 452. Ascan be seen from FIGS. 3a and 3b, however, none of the input lines forthe real side of the filter are kept negative for both the low-pass andhigh-pass configurations, so none of these lines are connected to theline 452. Some of the input lines must be weighted either negatively orpositively, depending upon whether the real side of the filter isconfigured as a high or low pass filter. These input lines (lines 436,438, 440, 444, 446, and 448) are connected to supply line 454 or supplyline 456, which are switched between positive and negative bias asrequired by the high or low pass configuration. The reference voltagelevel is supplied to lines 422-434 by line 458. Line 460 provides theinput sample signal for all the gates. An output electrode 461 isprovided for collecting the charge transferred through the real sideCCDs.

Similar connections are provided for the CCDs in the imaginary side ofthe filter. Thus lines 462-472 are used to apply the input samplingpulses to the imaginary half of the filter, the reference is applied tolines 474-484, and the signal is applied through lines 486-496. Anoutput electrode 497 collects the charge transferred through the CCDs inthe imaginary side of the filter.

The magnitude of the weighting applied to each signal is determined bythe size (active area) of the input gate for each signal sample, whilethe time delay of the injected sample is determined by the position inthe CCD of the cell at which that signal is injected. The length (numberof cells) of each CCD determines the amount of delay--the longer theCCD, the more delay.

FIG. 5 is a potential diagram illustrating the operation, at times T₁-T₄, of an input sampling scheme. This sampling scheme may be used inthe filters of this invention to inject weighted signal samples into aCCD. The sampling pulse is applied to the ohmic electrode while theinput signal (relative to the reference gate) is applied to the inputgate. Next to the input gate are the clocking gates (with the exceptionof the side injection implementation of input sampling, as discussedbelow with respect to FIG. 6, when an additional dump gate isintroduced). FIG. 5a depicts the potential diagram of the CCD inputsection at an instant (T₁) when the signal is not getting sampled. Uponthe application of a sampling pulse, as in FIG. 5b, the potential of theohmic region of the CCD, which acts as the source of signal electrons,changes as indicated by the arrows. The shaded area represents thepresence of charge (electrons). FIG. 5b shows the "fill" action whichoccurs when the region under the input gate is filled by an inflow ofelectrons from the ohmic region. The next action in this input samplingprocess is the "spill", as shown in FIG. 5c. As the sampling pulse isremoved (at a time T₃), any excess charge under the input gate spillsback into the ohmic region over the reference gate potential. This "filland spill" input sampling scheme thus meters an accurate amount ofcharge to form the signal charge packet under the input gate. Thischarge packet is linearly proportional to the signal potential (relativeto the reference gate potential). Once the signal charge packet has beencreated, it is transferred under the clocking gates either directly orthrough a dump gate, as shown by the dotted lines in FIG. 5d.

FIG. 6 is a plan view of an alternative mask layout for the half-bandfilter of FIG. 2. This layout is similar to that of FIG. 4, so that theclock lines 600-606, the real input lines 608-620, the real referencelines 622-634, the real signal lines 636-648, the supply lines 650-656,the reference voltage line 658, the input sample line 660, the imaginaryinput lines 662-672, the imaginary reference lines 674-684, and theimaginary signal lines 686-696 are all similar to the analogous elementsin the filter of FIG. 4. In the embodiment of FIG. 6, however, thefiltering is implemented with a combination of end injection signalsampling and side injection sampling. This approach requires additionaldump (side transfer) gates 698-712 to be provided for each sideinjection input site in the filter. Side injection is used for thoseinputs where the weighting factor is small enough to allow accommodationof the input gates within the location for phases 2 and 3 of the clockcycle. The multiple CCD layout is provided in this embodiment so thatend injection inputs can be used for the larger weighted signals. With alarger CCD, however, a larger number of signal inputs, each with smallerweights, could be included and thus side injection could be employed forall of the signal inputs. The charge transfer efficiency, however, whichis reduced for each extra stage in the CCD, imposes an upper limit onthis approach.

In conclusion, the filter of this inventions provides significantadvantages over the prior art techniques. In the present invention, forexample, any error in the injection of a particular weighted signal willnot affect any other weighted injection, whereas in a prior art tappedfilter, any error affects all the outputs which are tapped further downthe CCD. It has been shown that filters fabricated according to thisinvention can operate at clock rates in excess of 1 GHz with a chargetransfer efficiency of over 0.9999. The preferred embodiments of theinvention have been illustrated and discussed, but modifications andadditional embodiments will undoubtedly be apparent to those skilled inthe art. Furthermore, equivalent elements may be substituted for thoseillustrated and described herein, parts or connections might be reversedor otherwise interchanged, and certain features of the invention may beutilized independently of other features. Consequently, the examplespresented are not all inclusive, but are intended to teach those skilledin the art how to make and use the invention, while the appended claimsare more indicative of the full scope of the invention.

We claim:
 1. An analog transversal filter for processing an electricalsignal, comprising:a charge transfer delay line, including a pluralityof cells for storing electrical charge; a multiphase clock fortransferring electrical charge from cell to cell through the delay line;a plurality of injection electrodes, each electrode being connected to apredetermined one of the cells to sample the signal, weight the signalsample a predetermined amount, and inject a charge packet representingthe weighted signal sample into the cell; and an output electrode forcollecting and summing the charge packets transferred through the delayline.
 2. The filter of claim 1, wherein the weight applied to the signalsample by each injection electrode is directly proportional to the sizeof that electrode.
 3. An analog transversal filter for processing anelectrical signal, comprising:a plurality of charge transfer delaylines, each delay line including a plurality of cells for storingelectrical charge; a multiphase clock for transferring electrical chargefrom cell to cell through each delay line; a plurality of injectionelectrodes, each electrode being connected to one of the delay lines tosample the signal, weight the signal sample a predetermined amount, andinject a charge packet representing the weighted signal sample into thedelay line; and an output electrode for collecting and summing thecharge packets transferred through the delay lines.
 4. The filter ofclaim 3, wherein the weight applied to the signal sample by eachinjection electrode is directly proportional to the size of thatelectrode.
 5. An analog transversal filter for processing an electricalsignal, comprising:a charge transfer delay line, including a pluralityof stages, each stage including a plurality of cells for storingelectrical charge such that the cells of each stage are wider, in adirection transverse to the direction of charge transfer in the delayline, than the cells of preceding stages within the delay line; amultiphase clock for transferring electrical charge from cell to cellthrough the delay line; a plurality of injection electrodes, eachelectrode being connected to one of the stages to sample the signal,weight the signal sample a predetermined amount, and inject a chargepacket representing the weighted signal sample into the stage; and anoutput electrode for collecting and summing the charge packetstransferred through the delay line.
 6. A method of processing anelectrical signal through a charge transfer delay line including aplurality of cells for storing electrical charge, comprising the stepsof:sampling the signal at a predetermined rate; weighting the signalaccording to a predetermined weighting function; injecting a chargepacket representing the weighted signal sample into one of the cells;repeating the steps of weighting and injecting for a predeterminedplurality of the cells; applying the outputs of a multiphase clock tothe cells to transfer the charge packets through the delay line; andcollecting the summing the charge packets transferred through the delayline.
 7. A method of processing an electrical signal through a pluralityof charge transfer delay lines each having a plurality of cells forstoring electrical charge, comprising the steps of:sampling the signalat a predetermined rate; weighting the signal according to apredetermined weighting function; injecting a charge packet representingthe weighted signal sample into one of the delay lines; repeating thesteps of weighting and injecting for each delay line; applying theoutputs of a multiphase clock to the cells in each delay line totransfer the charge packets through the delay lines; and collecting andsumming the charge packets transferred through the delay lines.